H-1BSalary Explorer

R&D Engineer IC Design · San Jose, CA

R&D Engineer IC Design in San Jose, CA H-1B salaries

Employers filed 121 certified H-1B applications for R&D Engineer IC Design roles in San Jose, CA between Oct 2023 and Jun 2026. The median salary was $199,453, 15% above the median for this job across the US.

Median salary offered
$199,453
Middle half earn
$171,205 to $204,901
Top 10% earn over
$216,091
Certified filings
121

Pay by employer

Broadcom Corporation61$199,4530%$168,352 – $204,901
LSI Corporation33$199,4530%$180,003 – $204,901
Avago Technologies US Inc.26$202,870+2%$180,003 – $205,822
Brocade Communications Systems1$173,730−13%$173,730 – $173,730

By experience level

Level I1$124,197$127,230
Level II2$139,038$156,850
Level IV63$204,901$216,090

Levels run from entry level (I) to fully competent (IV). Minimum is the estimated prevailing wage for San Jose, CA.

By year

202310$180,003
202438$180,003
202552$202,870
202621$205,947

Latest filings

ReceivedLevel
2026-06-23Avago Technologies US Inc.$208,177–
2026-05-27Broadcom Corporation$208,177–
2026-05-19Brocade Communications Systems$173,730–
2026-05-14Avago Technologies US Inc.$173,730–
2026-05-13Broadcom Corporation$216,091IV
2026-05-04LSI Corporation$216,091IV
2026-04-30Broadcom Corporation$216,091IV
2026-04-21Broadcom Corporation$205,947–
2026-04-16Avago Technologies US Inc.$216,091IV
2026-03-24Broadcom Corporation$205,947–
2026-03-17LSI Corporation$216,091IV
2026-03-03Avago Technologies US Inc.$205,947–
2026-03-02Avago Technologies US Inc.$205,947–
2026-02-19Avago Technologies US Inc.$171,205–
2026-02-03Broadcom Corporation$171,205–
2026-01-23LSI Corporation$170,884–
2026-01-22Broadcom Corporation$216,091IV
2026-01-21LSI Corporation$216,091IV
2026-01-21Avago Technologies US Inc.$205,445–
2026-01-15Broadcom Corporation$146,939–
2026-01-13LSI Corporation$205,445–
2025-12-31Avago Technologies US Inc.$170,884–
2025-12-29LSI Corporation$170,884–
2025-12-29Broadcom Corporation$205,445–
2025-12-19LSI Corporation$216,091IV

The 25 most recent of 121. Every filing is on the San Jose, CA and R&D Engineer IC Design pages.

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